Compact, 2-tick carry, 2-wide, full adder

I have made some changes from the previous design due to slow carry propagation and sum. The main changes that made this possible were removing the final torch from my XOR gate and converting it to an XNOR gate. For the carry, this is then directly combined with the inverted carry in, in a NAND gate (carry NAND). This step is where the two-tick carry propagation occurs. Then the last component of the carry comes from the XNOR gate, which has already computed the AND of both A and B inputs; this is then directly ORed with the carry NAND output.

For the sum, a second XNOR gate is used. Wired with the output from the first XNOR and the carry input (which had to be un-inverted). This gives a sum speed of 4 ticks.

I have been able to tile this adder with a one-block gap between each adder. I will upload a schematic file for this on my minmev(RUBENHILLIER).